Process for making vertically-oriented interconnections for VLSI

Details Process for making vertically-oriented interconnections for VLSI Process for making vertically-oriented interconnections for VLSI

1987-06-02

1989-02-28

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437192, 437201, 437203, 437241, 437978, 437195, 148DIG20, 148DIG43, 148DIG114, H01L 21285, H01L 21318

Patent

active

048085529

ABSTRACT:
A process is disclosed for making a conductive interconnecting path formed between two conductive areas of an integrated circuit, the conductive areas separated by at least an insulating layer of silicon nitride over a layer of oxide. The interconnecting path is formed by depositing a thick insulator coating, over the conductive and non-conductive areas then forming a vertical-walled trench, with said silicon nitride acting as an etch stop, in the thick insulator between conducting areas, then filling the trench with conductive material using chemical vapor deposition, and finally removing conductive material except for that conductive material deposited in the trench.

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