Bi-CMOS logic gate circuits for low-voltage semiconductor integr

Details Bi-CMOS logic gate circuits for low-voltage semiconductor integr Bi-CMOS logic gate circuits for low-voltage semiconductor integr

1991-02-01

1992-09-08

Westin, Edward P.

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307446, 307454, 307451, 307443, H03K 19092, H03K 1902

Patent

active

051461188

ABSTRACT:
A Bi-CMOS logic gate circuit according to the present invention comprises a complementary Bi-CMOS output circuit at the output stage composed of a first-polarity bipolar transistor and a second-polarity bipolar transistor, and a level compensation circuit, provided between the input and output terminals of the Bi-CMOS output circuit, which compensates for each forward-bias voltage between the base and emitter of the first-polarity and second-polarity bipolar transistors. This arrangement allows the Bi-CMOS output circuit to swing the output voltage from the voltage of the high-voltage supply to that of the low-voltage supply at the output stage, previously smaller in the amplitude by the amount equal to the sum of the base-emitter voltage of two bipolar transistors.

REFERENCES:
patent: 4103188 (1978-07-01), Morton
patent: 4719370 (1988-01-01), Sugimoto
patent: 4727266 (1988-02-01), Fujii et al.
patent: 4779014 (1988-10-01), Masuoka et al.
patent: 4890016 (1989-12-01), Tanaka et al.
patent: 4902914 (1990-02-01), Masouka
patent: 5023478 (1991-06-01), Boudon et al.
patent: 5047669 (1991-09-01), Iwamura et al.
M. Fujishima et al., Novel BiCMOS Circuit Using Merged Device Structure, 1989 Spring National Convention Record, The Institute of Electronics, Information and Communication Engineers, C-274.

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