Method for fabricating a short channel trenched DMOS transistor

Details Method for fabricating a short channel trenched DMOS transistor Method for fabricating a short channel trenched DMOS transistor

Filed on

1994-08-11

Date issued

1995-12-12

Examiner

Quach, T. N.

Patent Class

Fishing, trapping, and vermin destroying

Other Related Categories

437154, 148DIG103, H01L 21336

Type

Patent

Status

active

Patent number

054749433

Description

ABSTRACT:
A DMOS transistor having a trenched gate is formed in a substrate such that the P body region of the transistor may be formed heavier or deeper while still maintaining a "short" channel. This is accomplished by forming a portion of the N+ type source region within the P body region prior to forming the trench, followed by a second implantation and diffusion of a relatively shallow extension of the N+ source region formed overlying a part of the P body region. The increased depth or doping concentration of the P body region advantageously lowers the resistance of the P body region, while the short channel lowers the on-resistance of the transistor for improved performance.

REFERENCES:
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patent: 5086007 (1992-02-01), Ueno
patent: 5168331 (1992-12-01), Yilmaz
Barbuscia, et al., pp. 757-760, IEDM., Dec. 1984 "Modeling of Polysilicon Dopant Diffusion for Shallow-Junction Bipolar Technology".
S. C. Sun et al., pp. 356-367, IEEE Trans. Electron Devices, vol. ED-27, Feb. 1980 "Modeling of the On-Resistance of LDMOS, VDMOS, and VMOS Power Transistors".

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