Method and apparatus for skewing a memory read clock signal in a

Details Method and apparatus for skewing a memory read clock signal in a Method and apparatus for skewing a memory read clock signal in a

1991-04-15

1993-10-19

Dixon, Joseph L.

Boots, shoes, and leggings

395550, 364DIG1, G06F 1202

Patent

active

052553833

ABSTRACT:
A method and a system for providing a skewed clock signal which is used for latching a data signal received from a memory into a read-data latch. A control signal latch and a control-signal buffer provide a control sign to the memory. A read-data buffer feeds a data signal from the memory to a read-data latch, which is provided with skewed read-clock signal. A read-clock delay circuit provides a clock signal to the read-data latch, and delays the read clock signal a period of time approximately equal to the signal propagation delay time of the read data buffer and the propagation delay time associated with transmitting a signal from the output terminal of said control signal latch circuit to the control-signal input terminal of the memory.

REFERENCES:
patent: 4901226 (1990-02-01), Barlow
patent: 4949249 (1990-08-01), Lefsky et al.
patent: 5113500 (1992-05-01), Talbott et al.

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