Method and apparatus for supporting a dual bit length protocol f

Details Method and apparatus for supporting a dual bit length protocol f Method and apparatus for supporting a dual bit length protocol f

1992-01-14

1993-10-19

Chun, Debra A.

Boots, shoes, and leggings

364DIG1, 3642304, 3642408, 364240, 3642403, G06F 1342

Patent

active

052553760

ABSTRACT:
An improved high speed bus and protocol are disclosed that are capable of transferring data in multiple modes. The bus is particularly useful in computer systems that require data transfer between a variety of computer peripheral memory devices. In base transfer mode, the bus is capable of a maximum of 32-bit data transfers while in extended transfer mode, the bus is capable of a maximum of 64-bit data transfers. The bus comprises a plurality of lines including address lines, size lines, data lines and various control lines. In its extended transfer mode, the bus is capable of employing a number of address and control lines as data transfer lines. The bus is also capable of disabling a device when the device is accessed in a transfer mode that the device does not support.

REFERENCES:
patent: 5109332 (1992-04-01), Culley
patent: 5109490 (1992-04-01), Arimilli et al.
patent: 5113369 (1992-05-01), Kinoshita

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