Sliced addressing multi-processor and method of operation

Details Sliced addressing multi-processor and method of operation Sliced addressing multi-processor and method of operation

1989-11-17

1993-03-23

Dixon, Joseph L.

Boots, shoes, and leggings

395300, 364749, 364786, 364787, G06F 1200, G06F 1500, G06F 733, G06F 750

Patent

active

051971402

ABSTRACT:
A multi-processor system arranged, in one embodiment, as an image and graphics processor. The processor is structured with several individual processors all having communication links to several memories. An addressing scheme, called sliced addressing, is used to spread contiguous related data over several memories so that the data can be concurrently accessed by several processors. A crossbar switch serves to establish the processor memory links. The entire image processor, including the individual processors, the crossbar switch and the memories, is contained on a single silicon chip.

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