Boots – shoes – and leggings
Patent
1985-09-13
1987-03-24
Zache, Raulfe B.
Boots, shoes, and leggings
G06F 1300
Patent
active
046529942
DESCRIPTION:
BRIEF SUMMARY
BACKGROUND OF THE INVENTION
The present invention relates to a system for transmitting data to an auxiliary memory device connected to a microprocessor.
Data transmission between a microprocessor and an external auxiliary memory device is conventionally performed by using a common random access memory (to be referred to as a common RAM hereinafter). Such a conventional system is shown by a block diagram of FIG. 1. Reference numeral 1 denotes a microprocessor (to be referred to as an MPU hereinafter) of a main device; and 2, an auxiliary memory device. The auxiliary memory device 2 has a data transmission/reception common RAM 4, data bus transceivers 5 and 6, and a memory medium 9 such as a magnetic disk. Reference numerals 7 and 8 denote buses, respectively.
With the above arrangement, when data is transmitted or received,
(1) the MPU 1 in the main device writes command data in the common RAM 4,
(2) the MPU 3 in the auxiliary memory device reads command data from the common RAM 4,
(3) the MPU 3 writes an execution result in the common RAM 4, and
(4) the MPU 1 reads the execution result from the common RAM 4.
Among operations (1) to (4), operations (1) and (2) or operations (3) and (4) are often simultaneously performed. In this case, when the MPUs 1 and 3 simultaneously access the common RAM 4, one of the MPUs is halted while the other MPU is being operated according to the conventional system. For example, access from the MPU 1 is performed while the operation of the MPU 3 is halted. When the operation of the MPU 1 is completed, the operation of the MPU 3 is started.
When one MPU must read or write access the common RAM 4 at high speed, this MPU must exclusively use the common RAM.
For example, when the MPU 3 in the auxiliary memory device 2 exclusively uses the common RAM 4 for direct memory access transfer, the MPU 1 in the main device must wait for a long period of time when it accesses the common RAM 4. As a result, the MPU 1 cannot perform other operations. In order to allow access of the common RAM 4 by the MPU 1 even during this period, data transfer from the MPU 3 is delayed, resulting in inconvenience.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a system having a plurality of common RAMs to decrease a wait time and to transmit data to or receive it from an auxiliary memory device at high speed.
It is another object of the present invention to provide a system for transmitting data to or receiving data from an auxiliary memory device, wherein when a main MPU and an auxiliary memory MPU simultaneously access an identical common RAM, one of the main and auxiliary memory MPUs has a priority over the other.
In order to achieve the above objects of the present invention, a plurality of data transmission/reception common RAMs are arranged in the auxiliary memory device, and a memory means is also provided for each common RAM to store an operating state of the corresponding common RAM. When the auxiliary memory device detects that a command is written by an external microprocessor in one of the common RAMs, the memory means corresponding to this common RAM is set, and data representing the operating state of the corresponding common RAM is stored in this memory means. When command processing is completed, the memory means is reset. The external microprocessor employs a system for transmitting data to or receiving data from the auxiliary memory device, so as to supply a command to a common RAM corresponding to a memory means which is not set, upon searching of the memory means (i.e., a common RAM which is not currently used by the auxiliary memory device). According to the present invention, there is also provided a priority order control circuit. A high-speed operation side is selected when the external microprocessor and the auxiliary memory device simultaneously access the identical RAM.
Since a plurality of common RAMs are provided, the main device microprocessor can exchange data with the auxiliary memory device at high speed. At the same time, continuous processi
REFERENCES:
patent: 4532587 (1985-07-01), Roskell et al.
Hattori Seiichi
Kanda Kunio
Fanuc Ltd
Zache Raulfe B.
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