Scan register and testing circuit using the same

Details Scan register and testing circuit using the same Scan register and testing circuit using the same

1990-09-27

1993-03-23

Beausoliel, Robert W.

Excavating

371 251, G01R 3128

Patent

active

051970708

ABSTRACT:
A scan path composed of a plurality of scan registers comprises a first test mode for testing a RAM, a second test mode for testing a logic circuit and a normal mode. In the first test mode, expected value data is set in each of latch circuits of the scan register. The expected value data held by the latch circuits are determined whether their logics coincide with data read from the RAM in a determination circuit. As a result of this determination, when a fault is occurring in the RAM, the logic of the data held by the latch circuit is inverted. In the second test mode, test data is set in each of latch circuits of the scan register, and the test data set are supplied to the logic circuit. In the normal mode, data read from the RAM is supplied to the logic circuit through the selector circuit without passing through the shift register. Accordingly, the delay time of data propagation path in the normal mode is extremely small and it does not degrade the speed performance of the semiconductor integrated circuit devices.

REFERENCES:
patent: 4926424 (1990-05-01), Maeno
patent: 4996691 (1991-02-01), Wilcox
patent: 5103450 (1992-04-01), Whetsel
Maeno et al., "Testing of Embedded Ram Using Exhaustive Random Sequences", IEEE Feb. 1987 International Test Conference, pp. 105-110.
Funatsu et al., "Designing Digital Circuits With Easily Testable Consideration", IEEE Nov. 1978 Semiconductor Test Conference, pp. 98-102.
Maunder et al., "Boundary-Scan, A Framework for Structured Design-for-Test", IEEE Feb. 1987 International Test Conference, pp. 714-723.

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