Method and apparatus for predicting the effective addresses of f

Details Method and apparatus for predicting the effective addresses of f Method and apparatus for predicting the effective addresses of f

1990-05-15

1993-05-11

Clark, David L.

Boots, shoes, and leggings

395375, 364DIG1, 3642318, 3642511, 3642551, 364263, 3642631, G06F 934, G06F 938

Patent

active

052108384

ABSTRACT:
A method and apparatus for loading a data value for a future LOAD instruction in a microprocessor by predicting the LOAD instruction's effective address. At each occurrence of a LOAD instruction, the effective address used is stored in a memory array which stores a last effective address and a next-to-last effective address. At a specified period before each LOAD instruction, the microprocessor loads a data value from a predicted effective memory address computed from the memory array. The predicted effective memory address is equal to the last effective address plus the difference between the last effective address and the next-to-last effective address. If the predicted effective address equals the actual effective address of the future LOAD instruction, the loaded data value is used.

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patent: 4918587 (1990-04-01), Pechter et al.
patent: 5007011 (1991-04-01), Murayama
patent: 5093777 (1992-03-01), Ryan

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