Method of producing insulated gate MOSFET employing polysilicon

Details Method of producing insulated gate MOSFET employing polysilicon Method of producing insulated gate MOSFET employing polysilicon

1989-02-27

1990-04-03

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 41, 437 44, 437148, 437150, 148DIG126, H01L 21265

Patent

active

049140477

ABSTRACT:
The present invention relates to a method of producing a vertical insulated gate field effect transistor. In the present invention a window portion is formed on a polysilicon layer which serves as a gate, by selectively etching the layer so as to leave the central portion intact. Ions of impurities are implanted while using the polysilicon layer having the window portion as a mask. Thereby a phase layer is formed and the ions of impurities are again implanted from the window portion, forming the N.sup.+ source region. Since this method is different from a conventional method in that positioning using a special resist mask is unnecessary, the N.sup.+ source region is formed by self alignment with a high efficiency and a high accuracy without any positional deviation caused by inaccurate positioning of a mask.

REFERENCES:
patent: 4443931 (1984-04-01), Baliga et al.
patent: 4680604 (1987-07-01), Nakagawa et al.
patent: 4680853 (1987-07-01), Lidow et al.
patent: 4774198 (1988-09-01), Contiero et al.
patent: 4810665 (1989-03-01), Chang et al.

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