Semiconductor memory device with dual reference elements

Details Semiconductor memory device with dual reference elements Semiconductor memory device with dual reference elements

1990-08-16

1993-03-23

Clawson, Jr., Joseph E.

Static information storage and retrieval

Floating gate

Particular biasing

365104, 365190, 365194, 365208, 365210, 3072968, 307449, G11C 1134

Patent

active

051970287

ABSTRACT:
The invention involves a semiconductor memory device having a memory cell with a drain, a gate and a source. The gate of the memory cell is supplied with a first potential for reading a memory cell data. A first reference line is connected to the drain of a first reference cell to receive a first reference cell data. A second reference cell has a drain, a gate and a source. A second reference line is connected to the drain of the second reference cell for receiving a second reference cell data. A gate voltage generating circuit having an output node is connected to the gate of the first reference cell for controlling the gate potential of the first reference cell so that the potentials at the first and second reference lines have the same power source voltage dependancy. A data detecting circuit reads the memory cell data in accordance with the comparison result between the potentials.

REFERENCES:
patent: 4223394 (1980-09-01), Pathak et al.
patent: 4467457 (1984-08-01), Iwahashi et al.
patent: 4611301 (1986-09-01), Iwahashi et al.
patent: 4868790 (1989-09-01), Wilmoth et al.
patent: 4884241 (1989-11-01), Tanaka et al.
patent: 4967394 (1990-10-01), Minagawa et al.

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