Hardware arrangement for floating-point addition and subtraction

Details Hardware arrangement for floating-point addition and subtraction Hardware arrangement for floating-point addition and subtraction

1991-10-31

1993-03-23

Mai, Tan V.

Boots, shoes, and leggings

364745, G06F 738

Patent

active

051970236

ABSTRACT:
A hardware arrangement for executing floating-point execution of addition and subtraction is supplied with two floating-point numbers each of which includes an exponential, a fraction represented by an absolute value and a sign bit indicating a sign of the fraction. The arrangement implements rounding on an execution result. In parallel operations, a floating-point execution is performed wherein no bit shifting is needed for normalization on an execution result of the two floating-point numbers. In parallel operations, a floating-point execution is performed wherein bit shifting to the right or the left by one bit is required for normalization on an execution result of the two floating-point numbers, and a floating-point execution wherein bit shifting to the left by more than two bits is required for normalization on an execution result of the two floating-point numbers. A selector is arranged to select an output of one of the first, second and third results according to upper bits of a result derived from executing the fractions in the first-mentioned floating-point execution.

REFERENCES:
patent: 4994996 (1991-02-01), Fossum et al.
patent: 4999803 (1991-03-01), Turrini et al.
patent: 5027308 (1991-06-01), Sit et al.
patent: 5063530 (1991-11-01), Ishikawa
patent: 5128889 (1992-07-01), Nakano
S. F. Anderson, The IBM System/360 Model 91: Floating-Point Execution Unit, IBM Journal--Jan. 1967, pp. 34-53.
American National Standard, IEEE Standard for Binary Floating-Point Arithmetic, Aug., 1985, pp. 7-18.
Computer Magazine, A Proposed Standard for Binary Floating-Point Arithmetic, The Institute of Electrical and Electronics Engineers, 1981.

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