Boots – shoes – and leggings
Patent
1990-10-17
1993-05-11
Mai, Tan V.
Boots, shoes, and leggings
364754, 364768, G06F 700
Patent
active
052107108
ABSTRACT:
A processor chip for adding a first integer having a plurality of groups of bits to a second integer having a plurality of groups of bits modulo a fourth integer having n-bits. The first integer plus the second integer equals a third integer. The processor chip includes a first register for storing the first integer, a second register for storing the second integer, and feedback register for storing a feedback number. The feedback number is the two's complement of the fourth integer. A plurality of full adders is coupled to the first register and the second register, and adds each group of bits of the first integer to the corresponding group of bits of the second integer, to generate the third integer. The bits of each group are added asynchronously during a time period. Sequentially, a second group of bits of the first integer are added to the corresponding second group of bits of the second integer. The processor chip also multiplies the first integer by the second integer wherein the full adders sequentially add each group of bits of the second integer to each corresponding group of bits of the third integer, in response to the least significant bit position of the first integer shifted right from the first register. The processor chip can exponentiate a first integer having n-bits by a second integer having m-bits, wherein the first integer raised to the power of the second integer equals a third integer. The exponentiation is preformed with successive applications of the multiplication operation.
REFERENCES:
patent: 3552374 (1970-07-01), Abrahamson et al.
patent: 3657476 (1972-04-01), Aiken
patent: 3781472 (1973-12-01), Goode et al.
patent: 3796830 (1974-03-01), Smith
patent: 3798359 (1974-03-01), Feistel
patent: 3868631 (1975-02-01), Morgan et al.
patent: 3876832 (1976-04-01), Morgan et al.
patent: 3958081 (1976-05-01), Ehrsam et al.
patent: 3962539 (1976-06-01), Ehrsam et al.
patent: 3979558 (1976-09-01), Peterson
patent: 4037093 (1977-07-01), Gregg et al.
patent: 4162480 (1979-07-01), Berlekamp
patent: 4200770 (1980-04-01), Hellman et al.
patent: 4218582 (1980-08-01), Hellman et al.
patent: 4251875 (1981-02-01), Marver et al.
patent: 4405829 (1983-09-01), Rivest et al.
patent: 4424414 (1984-01-01), Hellman et al.
patent: 4538240 (1985-08-01), Carter et al.
patent: 4567600 (1986-01-01), Massey et al.
patent: 4574361 (1986-03-01), Inagawa et al.
patent: 4587627 (1986-05-01), Omura et al.
patent: 4697248 (1987-09-01), Shirota
patent: 4891781 (1990-01-01), Omura
patent: 4918638 (1990-04-01), Matsumoto
patent: 4989171 (1991-01-01), Hollmann
Stewart, B. M., Theory of Numbers, The MacMillan Company, 1952 pp. 111-112, and 133-135.
Pohlig, Stephen C. and Martin E. Helman, "An Improved Algorithm for Computing Logarithms over GF(p) and Its Cryptographics Significance", IEEE Transactions on Information Theory, vol. IT-24, No. 1, Jan. 1978.
Abbruscato, C. R., "Data Encryption Equipment," IEEE Communications Magazine, vol. 22, No. 9, Sep. 1984.
Neuwirth, Lee, "A Comparison of Four Key Distribution Methods," Telecommunications, Jul., 1986.
Barrett, Paul, MSc (Oxon), "Implementing the Rivest Shamir and Adleman Public Key Encryption Algorithm on a Standard Digital Signal Processor," Computer Security Ltd, Aug., 1986).
Barney, Clifford, "Cypher Chip Makes Key Distribution a Snap," Electronics, Aug. 7, 1986.
Sedlak, H. and Golze, U. "An RSA Cryptography Processor," Institute for Theoretisch Informatik Technische University Braunschweig (no date available).
Matyas, Stephen M., "Public Key Registration" (no date available).
Rankie, Gordon, Dr., "Thomas-A Complete Single Chip RSA Device." (no date available).
Rivest, Ronald L., "RSA Chips (Past/Present/Future)," MIT Laboratory for Computer Science (no data available).
Kochanski, Martin, "Developing an RSA Chip," Business Simulations, Ltd. (no date available).
Brickell, Ernest F., "A Fast Modular Multiplication Algorithm with Application to Two Key Cryptography." (no date available).
Orton, G. A., Roy, M. P., Scott, P. A., Peppard, L. E., and Tavares, S. E., "VLSI Implementation of Public-Key Encryption Algorithms," Department of Electrical Engineering, Queen's University. (no date available).
Beth, T., Cook, B. M., and Gollmann, D., "Architectures for Exponentitation in GR(2.sup.n)." (no date available).
Diffie, W. and M. E. Hellman, "New Directions in Cryptography", IEEE Transactions on Information Theory, vol. IT-22, Nov. 1976, pp. 644-654.
Cylink Corporation
Mai Tan V.
LandOfFree
Modulo arithmetic processor chip does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Modulo arithmetic processor chip, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Modulo arithmetic processor chip will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1356193