Process for extracting logic from transistor and resistor data r

Details Process for extracting logic from transistor and resistor data r Process for extracting logic from transistor and resistor data r

1991-09-10

1993-05-11

Cosimano, Edward R.

Boots, shoes, and leggings

364578, G06F 1560

Patent

active

052106993

ABSTRACT:
A process for generating a logic netlist suitable for a logic simulator model from a data or netlist representation (11) of a circuit of transistors and resistors in either emitter coupled logic or current mode logic technology. The logic netlist is formed to serve as a logic simulation model having logic elements structured and patterned to follow the circuit representation at the transistor level, most commonly known as a netlist, which includes the resistors and the overall circuit interconnection. The logic extraction process (1.0, 2.0) identifies active and passive circuit elements connected according to prescribed criteria to eliminate elements which do not contribute to logic functionality as well as identifying elements essential to providing the logic functionality. A systematic approach keeps track of circuit nodes to enable the appropriate interconnection of logic elements patterned after the physical circuit represented as the netlist.

REFERENCES:
patent: 4342093 (1982-07-01), Miyoshi
patent: 4527249 (1985-07-01), Van Brunt
patent: 4594677 (1986-06-01), Barlow
patent: 4700187 (1987-10-01), Furtek
patent: 4703435 (1987-10-01), Darringer et al.
patent: 4715035 (1987-12-01), Boehner
patent: 4727545 (1988-02-01), Glackemeyer et al.
patent: 4745084 (1988-05-01), Rowson et al.
patent: 4763289 (1988-08-01), Barzilai et al.
patent: 4787061 (1988-11-01), Nei et al.
patent: 4803636 (1989-02-01), Nishiyama et al.
patent: 4831524 (1989-05-01), Furgerson
patent: 4939681 (1990-07-01), Yokomizo et al.
patent: 4942536 (1990-07-01), Watanabe et al.
patent: 4945503 (1990-07-01), Takasaki
patent: 4954953 (1990-09-01), Bush
patent: 5140526 (1992-08-01), McDermith et al.
"Minimization Technique for Series-Gate Emitter-Coupled Logic" by C. S. Choy and P. L. Jones, IEE Proceedings, vol. 136, Pt. G, No. 3, Jun. 1989, pp. 105-113.
"Auto-Synthesis of Series-Gated Emitter-Coupled Logic" by Choy, Sep. 18-19, 1989 IEEE, Paper 8.5, pp. 221-224.
"LOGEX--An Automatic Logic Extractor from Transistor to Gate Level for CMOS Technology" by Boehner, 25th ACM/IEEE Design Automation Conference, Paper 34.2, Jun. 12-15, 1988, IEEE, pp. 517-522.
"MIS: A Multiple-Level Logic Optimization System" by Brayton et al., IEEE Transactions on Computer-Aided Design, vol. CAD-6, No. 6, Nov. 1987, pp. 1062-1081.
"Advanced Structured Analysis and Design" by Peters, published by Prentice-Hall, 1987 pp. 69-100.

Affiliated with

Also associated with

Rating

Process for extracting logic from transistor and resistor data r does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Process for extracting logic from transistor and resistor data r, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for extracting logic from transistor and resistor data r will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1356021