Fishing – trapping – and vermin destroying
Patent
1994-09-28
1996-02-20
Fourson, George
Fishing, trapping, and vermin destroying
437235, 437241, H01L 2144, H01L 2148
Patent
active
054928656
ABSTRACT:
The invention relates to an integrated circuit including one or more amorphous silicon layers for neutralizing charges which occur in various dielectric layers during fabrication. The amorphous silicon layers include dangling silicon bonds which neutralize charges which would otherwise cause isolation breakdown, impair integrated circuit performance and increase manufacturing costs.
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Chang Kuang-Yeh
Jain Vivek
Nariani Subhash R.
Pramanik Dipankar
Everhart C.
Fourson George
VLSI Technology Inc.
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