Multilayer wiring method of on-chip modification for an LSI

Details Multilayer wiring method of on-chip modification for an LSI Multilayer wiring method of on-chip modification for an LSI

1991-08-23

1993-03-23

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437195, 437923, H01L 2180

Patent

active

051963620

ABSTRACT:
In interconnecting signal wires between circuit elements of a semiconductor integrated circuit chip having a multilayered wiring structure, the signal wires are divided or classified into a first group of signal wires with lower modification-requisite possibilty and a second group of signal wires with higher modification-requisite possibility. The first group of signal wires are allocated to a lower wiring layer and wired therein. Then, the second group of signal wires are allocated to an upper wiring layer and wired therein. The second group of signal wires are allocated to and connected in the upper wiring layer, so that a laser is allowed to be fired directly to the upper wiring layer for disconnecting the signal wire or a laser CVD is allowed to be easily implemented on the upper wiring layer for connecting the signal wire, thereby enhancing reliability of modification. The first group of signal wires not to be modified are allocated to and connected in the lower wiring layer. Those signal wires not to be modified thus do not become any obstacle to the connecting area of the upper wiring layers, thereby allowing efficient use of the wiring channels.

REFERENCES:
patent: 4259367 (1981-03-01), Dougherty, Jr.
patent: 4609809 (1986-09-01), Yamaguchi et al.
patent: 4868068 (1989-09-01), Yamaguchi et al.
patent: 4900695 (1990-02-01), Takahashi et al.
patent: 5043297 (1991-08-01), Suzuki et al.

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