Method of fabricating an integrated circuit for providing low-no

Details Method of fabricating an integrated circuit for providing low-no Method of fabricating an integrated circuit for providing low-no

1992-11-10

1993-10-19

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437133, 437912, 437184, 437126, 148DIG72, H01L 2170

Patent

active

052544923

ABSTRACT:
Generally, and in one form of the invention, an integrated circuit is disclosed for providing low-noise and high-power microwave operation comprising: an epitaxial material structure comprising a substrate 10, a low-noise channel layer 14, a low-noise buffer layer 16, a power channel layer 18, and a moderately doped wide bandgap layer 20; a first active region 24 comprising a first source contact 32 above the wide bandgap layer 22, a first drain contact 36 above the wide bandgap layer 22, wherein the first source contact 32 and the first drain contact 36 are alloyed and thereby driven into the material structure to make contact with the low-noise channel layer 14, and a first gate contact 28 to the low-noise buffer layer 16; and a second active region 26 comprising a second source contact 34 above the wide bandgap layer 22, a second drain contact 38 above the wide bandgap layer 22, wherein the second source contact 34 and the second drain contact 38 are alloyed and thereby driven into the material structure to make contact with the power channel layer 18, and a second gate contact 30 to the wide bandgap layer 22; wherein the first active region 24 and the second active region 26 are electrically isolated from one another, and whereby the integrated circuit is formed with all epitaxial layers formed during a single epitaxial growth cycle and is capable of providing low-noise, high-power, and switching operation at microwave frequencies.

REFERENCES:
patent: 4615102 (1986-10-01), Suzuki et al.
patent: 4635343 (1987-01-01), Kuroda
patent: 4641161 (1987-02-01), Kim et al.
patent: 4830980 (1989-05-01), Hsieh
patent: 4849368 (1989-07-01), Yamashita et al.
patent: 4952527 (1990-08-01), Calawa et al.
patent: 5021857 (1991-06-01), Suehiro
patent: 5041393 (1991-08-01), Ahrens et al.
patent: 5077231 (1991-12-01), Plumton et al.
patent: 5100831 (1992-03-01), Kuwata
patent: 5104825 (1992-04-01), Takikawa
patent: 5196359 (1993-03-01), Shih et al.

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