Method of manufacturing high and low voltage CMOS transistors on

Details Method of manufacturing high and low voltage CMOS transistors on Method of manufacturing high and low voltage CMOS transistors on

1993-02-23

1993-10-19

Thomas, Tom

Fishing, trapping, and vermin destroying

437 45, 437152, H01L 21266

Patent

active

052544877

ABSTRACT:
A semiconductor device where high voltage CMOS transistors and low voltage CMOS transistors are installed on a single chip, is manufactured by a silicon gate CMOS process. In order to reduce the number of repetitions of photolithographic process, low voltage N channel transistor domains and high voltage P channel transistor domains are simultaneously implanted by B ion, and low voltage P channel transistor domains and high voltage N channel transistor domains are simultaneously implanted by P ion.

REFERENCES:
patent: 4403395 (1985-09-01), Curran
patent: 4628341 (1986-12-01), Thomas
patent: 5024960 (1991-06-01), Haken
patent: 5047358 (1991-09-01), Kosiak et al.
patent: 5156989 (1992-10-01), Williams et al.
patent: 5158463 (1992-10-01), Kim et al.

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