Fishing – trapping – and vermin destroying
Patent
1993-04-19
1994-10-25
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 69, 437238, H01L 21302
Patent
active
053588908
ABSTRACT:
A process for forming isolation regions (20) having a self-aligned channel-stop (22) formed by implanting dopant atoms (24) through the isolation regions (22). An isolation mask (15) is formed over an active region (16) in a semiconductor substrate (10). The isolation mask can be constructed from a variety of materials including silicon nitride, silicon oxynitride, boron nitride, polysilicon, and germanium oxide. Thick isolation regions (20) are formed on either side of the isolation mask (15) and an ion implant process is carried out to form doped regions (22) in the substrate (10) immediately below the isolation regions (20). The isolation mask (15) prevents dopant atoms (24) from entering the active region (16) of the substrate (10).
REFERENCES:
patent: 4085498 (1978-04-01), Rideout
patent: 4277882 (1981-07-01), Crossley
patent: 4435895 (1984-03-01), Parrillo et al.
patent: 4494304 (1985-01-01), Yoshioka
patent: 4987093 (1991-01-01), Teng et al.
patent: 5024961 (1991-06-01), Lee et al.
patent: 5091332 (1992-02-01), Bohr et al.
patent: 5173438 (1992-12-01), Sandhu
patent: 5240874 (1993-08-01), Roberts
patent: 5242849 (1993-09-01), Sato
T. Nishihara, et al., "A 0.5 Micron Isolation Technology Using Advanced Poly Silicon Pad LOCOS (APPL)", IEEE-IEDM, 1988, 100-102.
H. Mikoshiba, et al., "A Novel CMOS Process Utilizing After-Gate-Implantation Process" pp. 41-42, VLSI Symp. 1986, San Diego, Calif.
R. Eklund, et al. "A 0.5 Micron BiCMOS Technology for Logic and 4Mbit-class SRAM's" IEEE-IEDM, 1989, 425-428.
K. Sunouchi, et al., "A Surrounding Gate Transitor (SGT) Cell for 64/256Mbit DRAMs" IEEE-IEDM, 1989, 23-26.
P. A. van der Plas, et al., "Field Isolation Process for Submicron CMOS", 19-20 1987 VLSI Symp., Karuizawa, Japan.
M. Seirodski, MeV Ion Implant Applications presentation--Genus General Ionex, Feb. 24, 1989.
K. Kanba, et al., "A 7 Mask CMOS Technology Utilizing Liquid Phase Selective Oxide Deposition" IEEE-IEDM, 1991, 637-640.
L. C. Parrillo, et al., "Twin-Tub CMOS II-An Advanced VLSI Technology" IEEE-IEDM, 1982, 706-709.
J. Hayden, et al., "A High-Performance Sub-Half Micron CMOS Technology For Fast SRAMS" IEEE-IEDM, 1989, 417-420.
Pfiester James R.
Sivan Richard D.
Chaudhuri Olik
Dockrey Jasper W.
Dutton Brian K.
Motorola Inc.
LandOfFree
Process for fabricating isolation regions in a semiconductor dev does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process for fabricating isolation regions in a semiconductor dev, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process for fabricating isolation regions in a semiconductor dev will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-135028