Semiconductor device having trench type structure

Details Semiconductor device having trench type structure Semiconductor device having trench type structure

1990-05-29

1991-07-16

Hille, Rolf

357 54, 357 55, 357 59, 357 51, H01L 2910, H01L 2978, H01L 2934, H01L 2906

Patent

active

050328824

ABSTRACT:
A semiconductor device comprises a P type semiconductor substrate (1) with a trench (12) formed on a main surface thereof. An N type drain region (15a) is formed at the bottom surface portion of the trench (12). An insulating layer (19c) is formed on the surface of the substrate (1) including a sidewall and the bottom surface of the trench (12), the layer having a hole (20b) whose bottom surface being at least the surface of the drain region (15a). A conductive layer (18) is formed on the insulating layer (19c) which is contact with the drain region (15a) at the bottom surface of the trench (12) through the hole (20b). The conductive layer (18) consititues a drain electrode. A gate (13) is interposed between the conductive layer (18) and the sidewall of the trench (12), formed along the sidewall of the trench (12) and insulated by the insulating layer (19c). An N type source region (15b) is formed on the surface of the substrate (1) including a portion of the sidewall of the trench (12). The drain electrode, the source electrode and the gate (13) constitute a MOS type field effect transistor (T2). At least a portion of a channel region is formed on the sidewall portion of the trench (12) between the drain region (15a) and the source region (15b). A capacitor (C2) is formed on the surface of the substrate (1) to be connected to the field effect transistor (T2).

REFERENCES:
patent: 4630237 (1986-12-01), Miura et al.
patent: 4683643 (1987-08-01), Kakajima et al.
patent: 4707457 (1987-11-01), Erb
patent: 4786953 (1988-11-01), Morie et al.
patent: 4845539 (1989-07-01), Inoue
"An Isolation-Merged Vertical Capacitor Cell for Large Capacity DRAM", Nakajima et al., IEDM-84, pp. 240-243.
"A New Soft-Error Immune DRAM Cell with a Transistor on a Lateral Epitaxial Silicon Layer", Kubota et al., IEDM-87, pp. 344-347.

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