Method of manufacturing an integrated high electron mobility tra

Details Method of manufacturing an integrated high electron mobility tra Method of manufacturing an integrated high electron mobility tra

1992-03-09

1994-10-25

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 96, 437184, 437912, H01L 21265

Patent

active

053588789

ABSTRACT:
A method of realizing an integrated circuit on a substrate (10) includes steps for forming a high electron mobility transistor (HEMT), including the realization of a superimposed structure (11) of layers on the substrate, among which are present at least a first layer (31) or channel of a material with a narrow bandgap and weakly doped, a second layer (22) or spacer of a material of wider bandgap and weakly doped, and a third layer (23) or donor of a material of wide bandgap and strongly doped, which layers are covered by a fourth layer (24) or Schottky layer, and the realization of an insulating zone completely surrounding the transistor relative to the other elements of the integrated circuit. For realizing the insulation, the method includes the formation at the surface of the superimposed layer structure of a mask (M) covering and defining the active zone of the transistor, etching of the superimposed layer structure down to the substrate (10) with underetching under the mask (M), so as to insulate the active zone by means of a mesa, the realization of a dielectric layer (K) by anisotropic deposition, directional etching of the dielectric layer (K) while the portions of this layer (K) protected by the mask (M) are maintained as a result of the under-etching and disposed on the flanks of the mesa around the active zone of the transistor, and removal of the mask (M).

REFERENCES:
patent: 4545109 (1985-10-01), Reichert
patent: 4663643 (1987-05-01), Mimura
GAAS IC. Symposium Tech. Digest, Oct. 1989, pp. 143-146 "Low Temp. Buffer AlInAs/GaInA5 on InP HEMT Technology for Ultra-High-Speed Integrated Cir.".

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