Programmable logic array adder

Details Programmable logic array adder Programmable logic array adder

1980-07-22

1982-09-07

Malzahn, David H.

Boots, shoes, and leggings

364716, G06F 750

Patent

active

043487360

ABSTRACT:
This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two-bit decoder for receiving each like order pairs of digits A.sub.i, B.sub.i of two n digit binary numbers A.sub.0, A.sub.1 . . . A.sub.n-1 and B.sub.0, B.sub.1 . . . B.sub.n-1 plus a carry C.sub.in. The decoders generate an output signal called a minterm on a different line for each of the four possible combinations A.sub.i .multidot.B.sub.i, A.sub.i .multidot.B.sub.i, A.sub.i .multidot.B.sub.i and A.sub.i .multidot.B.sub.i of the true and complement of each pair. The minterms from the decoders are fed to an array called the product term generator or AND array which generates product terms

REFERENCES:
patent: 3925652 (1975-12-01), Miller
patent: 3983538 (1976-09-01), Jones
patent: 3987287 (1976-10-01), Cox et al.
patent: 3993891 (1976-11-01), Beck et al.
patent: 4157590 (1979-06-01), Grice et al.
Brickman et al., "Programmable Logic Array One-Cycle Split Adder", IBM Tech. Disclosure Bulletin, vol. 17, No. 12, May 1975, pp. 3653-3655.

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