Multiple configuration memory circuit

Boots – shoes – and leggings

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364900, G06F 1200, G06F 1300

Patent

active

046176241

ABSTRACT:
A memory circuit to be connected to a central processing unit through an information bus and including a memory bank for storing several data words with each word having its own unique address, and including control circuitry enabling a user to obtain a data word having an address within a first address space in response to a first set of control signals and enabling the user to obtain a second data word having a second address contained within a second address space in response to a second set of control signals wherein the second address space are the addresses not included in the first address space. Also detailed is an embodiment that provides two modes of operation for a memory apparatus. In the first operational mode, the apparatus functions as a standard memory providing one word per address. In the second configuration, the memory provides a series of data words in accordance with the single address and an address incrementing signal.

REFERENCES:
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patent: 4280176 (1981-07-01), Tan
patent: 4473877 (1984-09-01), Tulk
Texas Instruments, Inc., "The TTL Data Book for Design Engineers", 2nd edition, 1981.
Texas Instruments, Inc., "1981 Supplement to the TTL Data Book for Design Engineers", 2nd edition, 1981.
Intel, "Microprocessor and Peripheral Handbook", 1983.
Eggegbrecht, "Interfacing to the IBM Personal Computer", 1983.
OKI Semiconductor, "MSM5832 Microprocessor Real-Time Clock/Calendar", 1982.
Monolithic Memories, "Programmable Array Logic Family", 1981.
INTERSIL, "ICL8240, ICL8250, ICL8260 Programmable Timers/Counters".
Texas Instruments, Inc., "Series 24 and 28 Standard, Low-Power, Power Down, Registered, Programmable, Read Only Memories", 1981.

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