Monolithically integrable MOS-comparator circuit

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H03M 136

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active

046175490

ABSTRACT:
An integrated semiconductor circuit for an analog-to-digital converter according to the parallel method, includes a multiplicity of identical comparators and a multiplicity of NOR gates. The comparators are addressable in a staggered manner at reference inputs thereof by a respective reference voltage and at signal inputs thereof jointly by a signal to be evaluated. Each of the comparators are respectively connected by a respective first signal output thereof to a first input of a respective one of the NOR gates forming a weighting stage with the respective comparator. The respective comparator is further connected by the respective first signal output thereof to a second input of another of the NOR gates associated with another of the comparators addressable by a next higher reference voltage. The respective comparator is also connected by respective second signal output thereof to a third input of a further one of the NOR gates associated with yet another of the comparators addressable by a next reference voltage. A read-only memory is provided and respective outputs of the NOR gates are connected via respective transfer transistors to respective inputs of the read-only memory. The transfer transistors are commonly connected to a signal transmitting device transmitting clock signals for controlling the outputs of the comparators and the transfer transistors are controlled by one of the clock signals serving for controlling the first signal outputs of the comparators.

REFERENCES:
patent: 4417233 (1983-11-01), Inoue
patent: 4449118 (1984-05-01), Dingwall
Peterson "A Monolithic Video A/D Converter", IEEE Journal of Solid-State Circuits, vol. SC-14, No. 6, Dec. 1979, pp. 932-937.
Dingwall "Monolithic Expandable 6 Bit 20 MHz CMOS/SOS A/D Converter", IEEE Journal of Solid-State Circuits, vol. SC-14, No. 6, Dec. 1979, pp. 926-932.

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