Semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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365174, G11C 1140

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active

043553753

ABSTRACT:
A semiconductor memory device includes a plurality of floating gate transistors each of which comprises a semiconductor substrate, a first and second impurity doped region, channel region formed between the first and second impurity doped regions, a floating gate electrode formed on the channel region and separated into a plurality of portions at an intermediate portion of the channel region, and, a control gate formed on the floating gate and on the intermediate portion of the channel region. Part of the control gate is formed between the separated floating gate electrode portions and faces the channel region.

REFERENCES:
patent: 4203158 (1980-05-01), Frohman-Bentchkowski et al.
patent: 4257056 (1981-03-01), Shum
"An Electrically Alterable Nonvolatile Memory Cell Using a Floating-Gate Structure", by D. C. Guterman et al., IEEE Journal of Solid State Circuits, vol. SC-14, No. 2, Apr. 1979, pp. 498-508.

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