Nonvolatile semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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Details

36518529, 36518511, 365201, G11C 1606

Patent

active

060943734

ABSTRACT:
This invention is made to reduce the circuit area and shorten the testing time by simplifying the construction of the control circuit and reducing the number of commands. In the automatic programming operation, PVOK is set to "0", EVOK and LCKOK are set to "1", and a memory cell is selected by an address latched in the address register. That is, the subroutine of a pre-program operation is effected with the address fixed. None of the subroutines of an erase operation and convergence operation are effected. In the erase operation, PVOK, EVOK and LCKOK are all set to "0" and memory cells are sequentially selected by the internal address of the address counter. That is, each of the memory cells selected by the internal address is subjected to the pre-program, erase and convergence operations.

REFERENCES:
patent: 5805510 (1998-08-01), Miyakawa et al.
patent: 5844843 (1998-12-01), Matsubara et al.

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