Stacked capacitor SRAM cell

Details Stacked capacitor SRAM cell Stacked capacitor SRAM cell

1991-01-30

1992-09-08

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 45, 437 52, H01L 21265, H01L 2170

Patent

active

051457997

ABSTRACT:
This is an SRAM cell and the cell can comprise: two NMOS drive transistors; two PMOS load transistors; first and second bottom capacitor plates 50, 52, with the first plate 50 being over a gate 34 of one of the drive transistors and the second plate 52 being over a gate 40 of another of the drive transistors; a layer of dielectric material 68 over the first and second bottom capacitor plates; and first and second top capacitor plates 20, 26 over the dielectric layer, with the first top capacitor 20 plate forming a gate of one of the load transistors and with the second top capacitor plate 26 forming a gate of another of the load transistors, whereby the capacitor plates form two cross-coupled capacitors between the gates of the drive transistors and the stability of the cell is enhanced. This is also a method of forming an SRAM cell.

REFERENCES:
patent: 4541006 (1985-09-01), Ariizumi et al.
patent: 4794561 (1988-12-01), Asu
patent: 4803534 (1989-02-01), Koike et al.
patent: 4890141 (1989-12-01), Tang et al.
patent: 4907057 (1990-03-01), Ariizumi et al.
patent: 5001539 (1991-03-01), Inoue et al.
"New Poly-Si PMOS Load (PPL) SRAM Cell Having Excellent Soft Error Immunity", Yamanaka et al., IEDM 1988, pp. 48-51.
"Influences on Soft Error Rates in Static Ram's", Carter et al., IEEE Journal of Solid State Circuits, vol SC-22, #3, 1987, pp. 430-436.

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