Method of minimizing dishing during chemical mechanical polishin

Details Method of minimizing dishing during chemical mechanical polishin Method of minimizing dishing during chemical mechanical polishin

1998-02-26

2000-07-25

Bowers, Charles

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

438692, 438633, 438697, 438687, 438631, 438672, 438638, 438668, H01L 21302

Patent

active

060936568

ABSTRACT:
A method is provided for eliminating the dishing effect of the chemical mechanical polishing (CMP) process on wide inlaid conductor leads in the layer of dielectric on a semiconductor device. A silicon dioxide dielectric having narrow and wide trenches is first coated with a blanket deposition of conductor material. The conductor material is coated with a photoresist and patterned with a reverse photo image of the trenches. The photoresist is etched leaving the photoresist over the trenches and the conductor material exposed between the trenches. The conductor material is etched removing the conductor material between the trenches and leaving the original thickness of conductor material over the trenches. The remaining photoresist is removed and the conductor material subject to CMP with the original thickness of conductor material acting to prevent dishing.

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