Single transistor EEPROM architecture

Details Single transistor EEPROM architecture Single transistor EEPROM architecture

1993-11-12

1994-09-06

Fears, Terrell W.

Static information storage and retrieval

Floating gate

Particular biasing

365 51, 365218, 365226, 365900, G11C 1140

Patent

active

053454189

ABSTRACT:
A single-transistor EEPROM device of the present invention comprises memory transistors in banks similar to NAND structures wherein the control gates of the memory transistors have negative voltages applied in various modes that allow reading, writing, and programming regardless of the V.sub.th of nonselected memory transistors in a bank. Programming and erasing results from various combinations of negative and positive voltages are used on the select gates together with positive voltages less than that alone which is necessary to induce Fowler-Nordheim tunneling are applied to the bit lines.

REFERENCES:
patent: 4758986 (1988-07-01), Kuo
patent: 4958321 (1990-09-01), Chang
patent: 4959812 (1990-09-01), Momodomi et al.
patent: 4962481 (1990-10-01), Choi et al.
patent: 4996571 (1991-02-01), Kume et al.
patent: 4996668 (1991-02-01), Paterson et al.
patent: 5197027 (1993-03-01), Challa
M. Momodomi et al., "New Device Technologies for 5V-Only 4Mb EEPROM with NAND-Structure Cell," IEDM Tech Dig., 1988, pp. 412-415.

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