Method for generating power slits

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364488, 395750, G06F 1560

Patent

active

053453948

ABSTRACT:
An automatic method of generating slits in power buses on a chip. The present invention includes three embodiments. The first embodiment is directed to a generic method of generating power slits. Once bus dimensions are identified, predetermined parameters for optimal power slit size and number are used to automatically generate a power slit layer for the mask database. The second embodiment is a continuation of the first embodiment and is directed to a method of generating power slits for an orthogonal corner case; where two buses overlap at 90.degree. angles. This is performed by locating all corner cases. Power slits are removed within a cross (corner/intersect) area of overlapping buses. At this point power slits from overlapping buses are extended across the corner/intersect area. The extension lines are logically ANDed together resulting in points within the corner/intersect area where the extension lines intersect. These intersection points indicate where new types of power slits, called "holes", can be generated. The third embodiment is directed to a method of generating power slits for non-orthogonal corner case. It is generally identical to the second embodiment.

REFERENCES:
patent: 4835705 (1989-05-01), Fujino et al.
patent: 5046017 (1991-09-01), Yujama et al.
patent: 5202578 (1993-04-01), Hideshima
patent: 5272645 (1993-12-01), Kawakami et al.

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