Patent
1997-09-15
2000-03-28
Teska, Kevin J.
39550006, G06F 1750
Patent
active
060442093
ABSTRACT:
A method and system for segmenting wires in the design stage of a integrated circuit to allow for the efficient insertion of an optimum quantity of buffers. The method begins by locating wires in the integrated circuit which interconnect transistors and then determining the characteristics of the transistor and the characteristics of the interconnecting wires. Next, the method computes a first upper limit for an optimum quantity of buffers utilizing total capacitive load wire and transistor characteristics, then the method computes a second upper limit for an optimum quantity of buffers assuming buffer insertion has decoupled the capacitive load. Finally, the method segments the wires by inserting nodes utilizing the greater of the first computation or the second computation. A determined upper limit on buffer quantity allows wires to be segmented such that the number of candidate buffer insertion topologies is manageable. Therefore, an optimum number of buffers can be efficiently inserted by buffer insertion method which utilize the segmented wires.
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Alpert Charles Jay
Devgan Anirudh
Quay Stephen Thomas
Dillon Andrew J.
Garbowski Leigh Marie
International Business Machines - Corporation
Salys Casimer K.
Teska Kevin J.
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