Metal working – Method of mechanical manufacture – Assembling or joining
Patent
1985-05-02
1986-10-14
Hearn, Brian E.
Metal working
Method of mechanical manufacture
Assembling or joining
29576W, 29578, 148DIG156, H01L 2126
Patent
active
046164022
ABSTRACT:
A method of manufacturing a semiconductor device with a stacked-gate-electrode structure which includes; forming source and drain regions in the surface portion of a semiconductor substrate in a spaced-apart relationship, forming a floating gate such that it overlies the channel region between the source and drain regions with a gate insulating film therebetween, and forming a control gate such that it overlies the floating gate with an insulating film therebetween. An oxidation-resistant film pattern having a predetermined opening is formed over a non-monocrystalline silicon layer. The non-monocrystalline silicon layer within the opening is selectively oxidized with the oxidation-resistant film pattern as a mask to form a separation insulating film. In this way, a floating gate layer is formed with the portion of the non-monocrystalline silicon layer insulatingly separated. With the oxidation-resistant film pattern left over the floating gate layer and with the separation insulating film left within the opening, a control gate layer is formed over the surface of the resultant surface to permit the whole surface of the resultant surface to be planarized.
REFERENCES:
patent: 4407696 (1983-10-01), Han et al.
patent: 4412310 (1983-10-01), Korsh et al.
patent: 4426764 (1984-01-01), Kosa et al.
patent: 4495693 (1985-01-01), Iwahashi et al.
patent: 4512074 (1985-04-01), Sasaki
patent: 4517732 (1985-05-01), Oshikawa
Jacobs et al., "n-Channel Sc-Gate Process for MNOS EEPROM Transistors," Solid State Electronics, vol. 24, pp. 517-522 (1981).
Chen, "Threshold-Alternable Si-Gate MOS Devices", IEEE Transactions Electron Dev., vol. ED-24, No. 5, May 1977.
Auyang Hunter L.
Hearn Brian E.
Kabushiki Kaisha Toshiba
LandOfFree
Method of manufacturing a semiconductor device with a stacked-ga does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of manufacturing a semiconductor device with a stacked-ga, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of manufacturing a semiconductor device with a stacked-ga will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1333414