Method of fabricating an insulated gate type field-effect transi

Metal working – Method of mechanical manufacture – Assembling or joining

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29576B, 29576W, 29591, 148187, H01L 21425, H01L 21445

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active

046164014

ABSTRACT:
A method of fabricating a MOS device is disclosed, in which, after formation of a gate electrode and source, drain regions, conductive material films are formed by selective CVD on the exposed surfaces of the gate electrode and source, drain regions. The conditions of the selective CVD are set such that the conductive material films formed on the source and drain regions partly overlay over the field insulating film adjacent to and surrounding the source and drain regions.

REFERENCES:
patent: 4016594 (1977-04-01), Shappir
patent: 4330931 (1982-05-01), Liu
patent: 4441247 (1984-04-01), Gargini et al.
patent: 4506434 (1985-03-01), Ogawa et al.
patent: 4510670 (1985-04-01), Schwabe et al.
patent: 4512073 (1985-04-01), Hsu
patent: 4521952 (1985-06-01), Riseman
IBM Technical Disclosure Bulletin, vol. 21, No. 3, Aug., 1978, pp. 1250-1251, New York, US: V. L. Rideout "Fabricating Low Resistance Interconnection Lines and FET Gates in a Single Step", p. 1251, last two paragraphs.
Applied Physics Letters, vol. 44, No. 12, Jun. 15th, 1984, pp. 1139-1141, New York, US; W. A. Metz et al.: "Electrical Properties of Selectively Deposited Tungsten Thin Film", p. 1139, paragraphs 2,5.

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