Non-volatile semiconductor memory device

Details Non-volatile semiconductor memory device Non-volatile semiconductor memory device

1998-12-23

1999-11-16

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

36518514, 36518518, 3651852, 36518521, G11C 1604

Patent

active

059869399

ABSTRACT:
There is disclosed a non-volatile semiconductor memory in which writing and erasing are easily controlled. When electrons are supplied to a floating gate while a memory cell is in a writing condition, a channel is off. Therefore, there is little capacitive coupling between a control gate, a source and a drain. Even when the electric potential of a word line is raised to vary the electric potential of the source and the drain, the electric potential of the control gate hardly varies. Moreover, when electrons are extracted from the floating gate while the memory cell is in an erasing condition, the channel is on. Therefore, a capacitive coupling is generated between the control gate and the source and the drain. When the electric potential of the word line is raised to vary the electric potential of the source and the drain, the electric potential of the control gate varies accordingly. Since the data value is determined by the variation in the electric potential of the control gate, a complicated control heretofore necessary for preventing excess erasing is unnecessary.

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