Wordline driver for semiconductor memory device

Static information storage and retrieval – Floating gate – Particular biasing

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Details

36523003, 36523006, G11C 1606

Patent

active

059869380

ABSTRACT:
A wordline driver for a memory device includes a row decoder decoding externally inputted row address signals and outputting a main decoding signal and a main decoding bar signal, a wordline drive decoder decoding two lowest bits among the row address signals and outputting a global decoding signal, a local wordline driver receiving first and second signals and outputting a local wordline driving signal in accordance with the global decoding signal corresponding to the wordline drive decoder, and a sub-wordline driver coupled to the wordline drive decoder and the local wordline driver and outputting a sub-wordline driving signal to a sub-wordline in accordance with the local wordline decoding signal from the local wordline driver, and the main decoding signal and the main decoding bar signal outputted from the row decoder.

REFERENCES:
patent: 5293342 (1994-03-01), Casper et al.
patent: 5696727 (1997-12-01), Tsukude et al.
patent: 5831924 (1998-11-01), Nitta et al.
Noda, K. et al., "A Boosted Dual Word-line Decoding Scheme for 256Mb DRAMs", 1992 Symposium on VLSI Circuits Digest of Technical Papers, pp. 112-113, 1992.

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