Wafer burn-in test circuit for a semiconductor memory device

Details Wafer burn-in test circuit for a semiconductor memory device Wafer burn-in test circuit for a semiconductor memory device

1997-12-23

1999-11-16

Nelms, David

Static information storage and retrieval

Read only systems

Fusible

365201, 36523006, G11C 1700

Patent

active

059869178

ABSTRACT:
A semiconductor memory device has independently controllable word lines, thereby allowing various background data patterns to be freely written to the memory cells to perform various wafer burn-in tests. This allows the leakage between adjacent memory cells to be efficiently tested by independently controllable word line activation signals, as well as the reliability of bit lines. A wafer burn-in test circuit for performing this improved burn-in test improves the reliability of the device by performing a level transition on the signals that drive the sub word line drivers, thereby eliminating the need to apply a high voltage to one transistor in the sub word line driver.

REFERENCES:
patent: 5590079 (1996-12-01), Lee et al.
patent: 5638331 (1997-06-01), Cha et al.
patent: 5654930 (1997-08-01), Yoo et al.

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