Single-poly flash memory cell for embedded application and relat

Details Single-poly flash memory cell for embedded application and relat Single-poly flash memory cell for embedded application and relat

1998-06-17

2000-03-28

Nelms, David

Static information storage and retrieval

Floating gate

Particular biasing

3651851, 36518526, 36518533, G11C 1604

Patent

active

06044018&

ABSTRACT:
A single-poly flash memory cell manufacturable by a standard CMOS fabrication process. A NMOS floating gate (32) is electrically connected to a PMOS floating gate (34). Both gates are fabricated in a single polysilicon process and form a flash memory cell. The floating gates are programmed by Vcc to the source (14) and drain (26) of the NMOS device (28), while applying about -Vcc to the source (20) of the PMOS device (30). Band-to-band hot electrons charge the floating gates. Biasing the NMOS device to operate as a FET allows the charge state of the gate to be sensed from the source current drawn. The memory cell is erased by applying a moderately high voltage to the source (14) NMOS device while negatively biasing the drain (22) of the PMOS device. In a particular embodiment, an integrated circuit device includes a CMOS circuit and a single-poly flash memory circuit. In a further embodiment, a DC-DC on-chip voltage converter produces the erase voltage from conventional CMOS voltage supplies.

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Katsuhiko Ohsaki, et al. A Single Poly EEPROM Cell Structure for Use in Standard CMOS Processes, IEEE Journal of Solid-State Circuits, vol. 29, No. 3. 311-316 (Mar. 1994).

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