Virtual bus for distributed hardware simulation

Details Virtual bus for distributed hardware simulation Virtual bus for distributed hardware simulation

1996-03-22

1999-03-09

Teska, Kevin J.

G06F 9455

Patent

active

058812679

ABSTRACT:
Virtual bus stubs, which can be distributed among constituent computers of a computer network, and a central resolver cooperate to simulate a bus which is connected between multiple circuit parts of a simulated circuit. With each simulated cycle of a clock of the bus, the resolver (i) collects data from the virtual bus stubs representing signals driven on the bus by one or more of the circuit parts, (ii) resolves the current simulated state of the bus from the collected data, and (iii) sends data representing the resolved current simulated state of the bus to the virtual bus stubs. As a result, the virtual bus stubs and the resolver collectively accurately simulate the bus connecting the circuit parts. Since each circuit part has access to the simulated state of the bus through a respective virtual bus stub, each circuit part has access to all information regarding the simulated state of simulated circuit which is necessary for the accurate simulation of each circuit part. Busses provide a convenient organization for division of parts of a model of the circuit. The bus protocol provides a convenient protocol for exchange of information between simulated circuit parts since the bus protocol is an inherent part of any simulation of each of the circuit parts. In addition, since the circuit parts communicate with one another exclusively through the bus, each circuit part requires no information regarding the state of the other circuit part beyond the state of the bus. Thus, the state of the bus includes all the information about each of the circuit parts and to which each other of the circuit parts requires access.

REFERENCES:
patent: 4821173 (1989-04-01), Young et al.
patent: 4937827 (1990-06-01), Beck et al.
patent: 5185865 (1993-02-01), Pugh
patent: 5327361 (1994-07-01), Long et al.
patent: 5455928 (1995-10-01), Herlitz
Ososanya et al., VLSI Design of a Bus Arbitration Module for the 68000 Series of Microprocessors, IEEE, pp. 398-402, Apr. 10, 1994.
Coelho, A VHDL Standard Package for Logic Modeling, IEEE, pp. 25-32, Jun. 1990.
Taub, Corrected Settling Time of the Distributed Parallel Arbiter, IEEE, pp. 348-354, Jul. 1992.

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