Patent
1996-11-27
1999-03-09
Beausoliel, Jr., Robert W.
G06F 1127
Patent
active
058812172
ABSTRACT:
Method for decoding inputs in a programmable state machine, including the following steps: bit-wise comparing state machine inputs with select information to produce bit-wise comparison results; determining the logical AND of the bit-wise comparison results; and determining the logical EXCLUSIVE OR of a negate indicator and the logical AND. In a further embodiment, a step of bit-wise ORing the comparison results with mask information is performed before the logical AND step. Circuitry for implementing the method: A bit-wise comparator has two sets of inputs. Its first set of inputs is coupled to state machine input signals. Its second set of inputs is coupled to select information. It is operable to produce bit-wise comparator outputs that indicate the results of bit-wise comparing the state machine input signals with the select information. AND circuitry has an AND circuitry output to indicate the logical AND of the comparator outputs. An EXCLUSIVE OR gate has its first input coupled to the AND circuitry output and has its second input coupled to a negate indicator. The output of the EXCLUSIVE OR gate constitutes the output of the inventive input comparison circuitry. In further embodiments, bit-wise OR circuitry may be interposed between the comparator and the AND circuitry. Such bit-wise OR circuitry may be used for masking by coupling its first set of inputs to the comparator outputs and coupling its second set of inputs to mask information. In the latter embodiment, the bit-wise results of the OR circuitry are ANDed by the AND circuitry.
REFERENCES:
patent: 3947823 (1976-03-01), Padegs et al.
patent: 4303990 (1981-12-01), Seipp
patent: 4425643 (1984-01-01), Chapman et al.
patent: 4431928 (1984-02-01), Skokan
patent: 4433413 (1984-02-01), Fasang
patent: 4446514 (1984-05-01), Brown et al.
patent: 4491907 (1985-01-01), Koeppen et al.
patent: 4500993 (1985-02-01), Jacobson
patent: 4598385 (1986-07-01), Kessels et al.
patent: 4622669 (1986-11-01), Pri-Tal
patent: 4674089 (1987-06-01), Poret et al.
patent: 4841232 (1989-06-01), Graham et al.
patent: 4868822 (1989-09-01), Scott et al.
patent: 4873666 (1989-10-01), Lefebvre et al.
patent: 4879646 (1989-11-01), Iwasaki et al.
patent: 4910417 (1990-03-01), El Gamal et al.
patent: 4912630 (1990-03-01), Cochcroft, Jr.
patent: 4924468 (1990-05-01), Horak et al.
patent: 4933897 (1990-06-01), Shankar et al.
patent: 4935719 (1990-06-01), McClure
patent: 4964033 (1990-10-01), Williams
patent: 4993027 (1991-02-01), McGraw et al.
patent: 5053700 (1991-10-01), Parrish
patent: 5059942 (1991-10-01), Burrows
patent: 5136590 (1992-08-01), Polstra et al.
patent: 5157673 (1992-10-01), Feldbrugge
patent: 5157781 (1992-10-01), Hardwod et al.
patent: 5173619 (1992-12-01), Gaudenzi et al.
patent: 5202976 (1993-04-01), Hansen et al.
patent: 5206948 (1993-04-01), DeAngelis et al.
patent: 5210862 (1993-05-01), DeAngelis et al.
patent: 5226149 (1993-07-01), Yoshida et al.
patent: 5226153 (1993-07-01), DeAngelis et al.
patent: 5317711 (1994-05-01), Bourekas et al.
patent: 5327435 (1994-07-01), Warchol
patent: 5345580 (1994-09-01), Tamaru et al.
patent: 5375228 (1994-12-01), Leary et al.
patent: 5400345 (1995-03-01), Ryan, Jr.
patent: 5418452 (1995-05-01), Pyle
patent: 5425036 (1995-06-01), Liu et al.
patent: 5442641 (1995-08-01), Beranger et al.
patent: 5450349 (1995-09-01), Brown, III et al.
patent: 5452437 (1995-09-01), Richey et al.
patent: 5473754 (1995-12-01), Folwell et al.
patent: 5475815 (1995-12-01), Byers et al.
patent: 5479652 (1995-12-01), Dreyer et al.
patent: 5488688 (1996-01-01), Gonzales et al.
patent: 5504755 (1996-04-01), Nozuyama
patent: 5519715 (1996-05-01), Hao et al.
patent: 5526365 (1996-06-01), Whetsel
patent: 5528526 (1996-06-01), Klug et al.
patent: 5530804 (1996-06-01), Edgington et al.
patent: 5532174 (1996-07-01), Corrigan
patent: 5534798 (1996-07-01), Phillips et al.
patent: 5535331 (1996-07-01), Swoboda et al.
patent: 5541935 (1996-07-01), Waterson
patent: 5548775 (1996-08-01), Hershey
patent: 5550528 (1996-08-01), Offord et al.
patent: 5555428 (1996-09-01), Radigan et al.
patent: 5557619 (1996-09-01), Rapoport
patent: 5561761 (1996-10-01), Hicok et al.
patent: 5564041 (1996-10-01), Matsui et al.
patent: 5566300 (1996-10-01), Naoe
patent: 5579251 (1996-11-01), Sato
patent: 5579492 (1996-11-01), Gay
patent: 5586288 (1996-12-01), Dahlberg
patent: 5590354 (1996-12-01), Klapproth et al.
patent: 5598421 (1997-01-01), Tran et al.
patent: 5606564 (1997-02-01), Ho et al.
patent: 5606710 (1997-02-01), Hall et al.
patent: 5613144 (1997-03-01), Hall et al.
patent: 5623500 (1997-04-01), Whetsel, Jr.
patent: 5630048 (1997-05-01), LaJoie et al.
patent: 5640508 (1997-06-01), Fujiwara et al.
patent: 5640542 (1997-06-01), Whitsel et al.
patent: 5644609 (1997-07-01), Bockhaus et al.
patent: 5699516 (1997-12-01), Sapir et al.
Montessoro et al. "General and Efficient Multiple List Traversal for Concurrent Fault Simulation", 1991 IEEE, pp. 43-48.
Marchioro et al. "Simulation of a Macro-pipelined Multi-CPU Event Processor for Use in Fastbus", 1989 IEEE, pp. 1597-1601.
Brockmann Russell C.
Ranson Gregory L.
Baderman Scott T.
Beausoliel, Jr. Robert W.
Hart Kevin M.
Hewlett--Packard Company
LandOfFree
Input comparison circuitry and method for a programmable state m does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Input comparison circuitry and method for a programmable state m, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Input comparison circuitry and method for a programmable state m will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1330041