Method of manufacturing vertical DMOS transistor with high off-b

Details Method of manufacturing vertical DMOS transistor with high off-b Method of manufacturing vertical DMOS transistor with high off-b

1993-11-23

1994-09-06

Fourson, George

Fishing, trapping, and vermin destroying

437203, 437958, 148DIG50, H01L 2144

Patent

active

053447891

ABSTRACT:
A semiconductor device includes an N.sup.- type semiconductor layer (2). The N.sup.- type semiconductor layer (2) includes a triangular pole trench (10), an apex portion thereof contains a gate electrode (5). The trench (10) penetrates the semiconductor layer (2) and a P type well region (3) and projects into an N.sup.+ type source region (4). A source electrode (7) is disposed so as to be insulated from the semiconductor layer (2) by an oxide film (9) and in contact with the well region (3) and the source region (4). A drain electrode (8) is connected to the semiconductor layer (2) through an N.sup.+ type semiconductor substrate (1). With higher potential at the gate electrode (5) than at the source electrode (7), the well region (3) is partially inverted into N type near the trench (10). Thus, the semiconductor device is turned on due to a channel created associated to the conductivity type inversion. Most of current flow allowed in the semiconductor layer (2) by the channel flows near the trench (10).
Hence, even when process patterns are refined, electrode-to-electrode insulation remains undegraded in the semiconductor device, attaining low on-resistance and nigh off-breakdown voltage.

REFERENCES:
patent: 4326332 (1982-04-01), Kenney
patent: 4374455 (1983-02-01), Goodman
patent: 4914050 (1990-04-01), Shibata
patent: 4937202 (1990-06-01), Maas
patent: 5023196 (1991-06-01), Johnson et al.
Chang, T. and D. Critchlow, "Vertical Fet RAM with deep trench isolation," IBM Tech. Dis. Bulletin, IBM Corp., 1980.

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