Clock signal control apparatus for data output buffer

Details Clock signal control apparatus for data output buffer Clock signal control apparatus for data output buffer

1998-03-16

2000-03-28

Lam, Tuan T.

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

365233, G11C 700

Patent

active

060436972

ABSTRACT:
A clock signal control apparatus for a data output buffer that controls a data access time and an output signal maintaining time of the data output buffer based on a period of an input first clock signal. The apparatus includes a clock signal generator for generating a second clock signal having a period controlled by a period of a first clock signal, a clock signal controller and a data output buffer. The clock signal controller delays the second clock signal from the clock signal generator for a predetermined time, generates an output enable signal and a third clock signal in accordance with the second clock signal. A data output buffer receives a data signal, buffers the data signal in accordance with the third clock signal and the output enable signal from the clock signal controller, and generates an output data signal. The second clock signal has one of a plurality of periods based on the first clock signal.

REFERENCES:
patent: 5532961 (1996-07-01), Mori et al.
patent: 5627794 (1997-05-01), Lee
patent: 5687134 (1997-11-01), Sugawara et al.
patent: 5764584 (1998-06-01), Fukiage et al.
patent: 5815462 (1998-09-01), Konishi et al.
patent: 5844846 (1998-12-01), Jang

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