Excavating
Patent
1998-01-20
1999-07-20
Canney, Vincent P.
Excavating
G06F 1100
Patent
active
059264853
DESCRIPTION:
BRIEF SUMMARY
TECHNICAL FIELD
This invention relates to a semiconductor test system having a simultaneous test function for testing a plurality of semiconductor memories that need repeated write cycles such as flash memories, and more particularly, to a semiconductor test system which is able to reduce the test time when writing the memories.
BACKGROUND ART
A semiconductor test system tests various types of semiconductor devices. One of the semiconductor devices is a flash EEPROM (Electrically Erasable Programmable Read Only Memory) that is a semiconductor IC memory. Further, in a semiconductor test system, in order to improve cost performance and test efficiency, a simultaneous test is frequently used in which a plurality of semiconductor devices are tested at the same time.
In a flash EEPROM, a time length (the number of times) required for writing data therein differs due to the structure of the memory cells. Thus, one writing process may not complete the data storage in a memory cell. In this type or memory, a write process of several cycles (re-write process) are usually necessary, and based on that re-write process, the memory is tested as to whether the memory device as a whole functions correctly or not. In other word, only a first write process will not necessarily be enough to evaluate the quality of the memory under test. Thus, after each of the write processes, the memory device is tested and if the device is determined acceptable, the test is continued for the remaining memory devices by repeatedly writing the data therein. The number of times for writing the data in the memory is predetermined based on the specification of the memory devices.
When testing a plurality of such re-write memory devices simultaneously by a semiconductor IC test system, the comparison result of each device is fed back to a control circuit for each channel corresponding to the device as a re-write inhibit signal so as to prevent excessive writing or erasing repetitions, which will improve reliability of the memory devices.
In the foregoing conventional technology, the memory devices are tested by performing the re-write process in an address by address manner to determine the pass/fail of the memory device.
In recent years, NAND type flash memories are newly introduced in the market as one of the flash memories. The NAND type flash memory can be re-written and evaluated as to pass/fail as a unit of page or byte. Therefore, the NAND type flash memory is distinguished from the conventional NOR type flash memory which is re-written address by address as a unit of bit.
FIG. 2 shows an example of semiconductor test system known to the inventor which has a simultaneous test function for testing a plurality of semiconductor memory devices that can be re-written. As shown in FIG. 2, the output signal of the memory device under test is applied to a pass/fail judgement circuit 1. A fail detection signal from the pass/fail judgement circuit 1 is selected by a selector 2 to match the corresponding channel of the test system based on the structural conditions of the memory device under test. For instance, the fail signal is selected and output according to the bit structure of input and output of the devices, such as 4 bit, 8 bit, . . . 18 bit and the like.
The fail signal is latched by a flip-flop 3 with a timing of a clock signal 101 for each address of the memory device. A logical AND is performed for the fail signal and a reference clock MCLK1 by an AND gate 4. A high level is fixedly provided at the data input terminal of a flip-flop 5. The flip-flop 5 is triggered by the output signal of the AND gate 4 to save this fail information. In an AND gate 6, the output signal of the flip-flop 5 passes therethrough when a write prohibition mode is activated. A selector 7 selects a channel for which the re-write operation should be prohibited. The timing is then adjusted by a clock signal MCLK2 by a flip-flop 8 and is output from a re-write control circuit 100 as a prohibition signal 102.
When the simultaneous test is carried out, the re-writ
REFERENCES:
patent: 5835436 (1998-11-01), Ooishi
patent: 5844849 (1998-12-01), Furutani
Advantest Corp.
Canney Vincent P.
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