Priority encoder applicable to large capacity content addressabl

Details Priority encoder applicable to large capacity content addressabl Priority encoder applicable to large capacity content addressabl

1993-01-07

1996-09-10

Ray, Gopal C.

Boots, shoes, and leggings

395732, 395435, 3642591, 3642599, 364DIG1, G06F 700

Patent

active

055553974

ABSTRACT:
A priority encoder is provided with priority circuitry for sequentially producing priority-ordered output signals and encoding circuitry for encoding the output signal. Small input, small unit priority circuits are used to form the priority circuitry into a hierarchical structure. An OR output of a small unit priority circuit in a lower hierarchy is used as an input signal of another small unit priority circuit in a higher hierarchy. An output signal of the priority circuit in the higher hierarchy has an address which corresponds to the address of the one input signal and is made an enable signal of the priority circuit in the lower hierarchy. The priority encoder, though simple in structure and formed with a small number of elements, operates at a high speed. Moreover, an encoder with a prefetch circuit is built into the priority encoder provided for a CAM block. While a "hit" signal in a first priority subblock is being encoded, a hit signal in a second priority subblock can be stored in the prefetch circuit. Therefore, the encoding operation is performed without subblock-to-subblock switch time, making the encoder best suitable for a large capacity, high speed CAM.

REFERENCES:
patent: 3928789 (1975-12-01), Elias
patent: 4293849 (1981-10-01), Lacy
patent: 4879561 (1989-11-01), Inkol
patent: 4887084 (1989-12-01), Yamaguchi
patent: 5036486 (1991-07-01), Noguchi et al.
patent: 5123105 (1992-06-01), Wyland et al.
patent: 5321640 (1994-06-01), Anderson et al.
"Design of CMOS VLSI", edited by Tetsuya Iizuka and supervised by Takuo Sugano, Baifukan 1989, pp. 176-177.
Hamamoto et al, "A 288KBit Fuly Parallel Content Addressable Memory Using Stacked Capacitor Cell Structure"; LSI Research and Development Laboratory, Mitsubishi Electric Corporation, 1991; pp. 205-208.

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