System for memory table cache reloads in a reduced number of cyc

Details System for memory table cache reloads in a reduced number of cyc System for memory table cache reloads in a reduced number of cyc

1995-05-24

1996-09-10

An, Meng-Ai T.

Boots, shoes, and leggings

395483, 3642434, 3642602, 364DIG1, 3649642, G06F 1200, G06F 1300

Patent

active

055553958

ABSTRACT:
A method and apparatus for reducing the latency of TLB and segment descriptor reloads by eliminating the extra read/write cycles normally required for these accesses. The CPU includes special cycles which perform segment descriptor and TLB reloads using only one cycle. The memory controller includes logic which returns the requested data back to the processor and, in addition, performs the required status bit modification. Therefore, the read/write cycle that was required in prior art designs to perform this status update is not required, but rather only a single read cycle is necessary to perform the same operation. In one embodiment, the memory controller includes logic which only performs the write to set the respective status bits in the case where the appropriate bits are not already set. This reduces the latency of subsequent memory cycles. In another embodiment, the memory controller asserts a completion signal back to the CPU to indicate that it has updated the status bits in the respective entry. If the CPU does not receive this signal, then it assumes the status update has not been performed and it performs a read/write cycle to set the respective status bits. This allows use of the present invention with prior art memory controllers as well as the caching of TLB and descriptor entries in the CPU cache.

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Clements, "Microprocessor System Design," 1992, 466-532.

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