Static information storage and retrieval – Floating gate – Particular biasing
Patent
1997-09-30
1999-03-09
Nelms, David
Static information storage and retrieval
Floating gate
Particular biasing
36518503, 36518533, 36518519, G11C 1606
Patent
active
058809937
ABSTRACT:
To check the programming of a nonvolatile memory cell storing an actual threshold value, the drain terminal of the cell is biased at a constant voltage; the gate terminal is biased at a check voltage; the cell is supplied with a predetermined current to determine a gate-source voltage drop related to the actual threshold value; and the voltage at the source terminal is supplied to an input of an operational amplifier. In an open-loop configuration, the desired threshold value of the set predetermined current is supplied as the check voltage; the amplifier compares the source voltage with the ground; and switching of the amplifier indicates the desired threshold value has been reached. In a closed-loop configuration, the output of the operational amplifier is connected directly to the gate terminal of the cell, and supplies the desired threshold value directly.
REFERENCES:
patent: 4758749 (1988-07-01), Rapp
patent: 5684741 (1997-11-01), Talreja
patent: 5699296 (1997-12-01), Song
M. Bauer et al., "A Multilevel-Cell 32 MB Flash Memory", IEEE International Solid-State Circuits Conference, Session 7, Flash Memory, Paper TA 7.7; pp. 98-99, 132-133; Feb. 16, 1995.
Kyu-hyoun Kim and Kwyro Lee, "A True Nonvolatile Analog Memory Cell Using Coupling-Charge Balancing," 1996 IEEE International Solid-State Circuits Conference, Session 16, Technology Directions: Memory, Paper FP 16.5; pp. 218-219, 268-269; Feb. 9, 1996.
Hieu Van Tran et al., "A 2.5V 256-Level Non-Volatile Analog Storage Device Using EEPROM Technology," 1996 IEEE International Solid-State Circuits Conference, Session 16, Technology Directions: Memory, Paper FP 16.6; pp. 220-221, 270-271; Feb. 9, 1996.
Chris Diorio et al., "A High-Resolution Non-Volatile Analog Memory Cell," 1995 IEEE International Symposium on Circuits and Systems, Apr. 1995.
Douglas A. Mercer, "A 14-b 2.5 MSPS Pipelined ADC with On-Chip EPROM," IEEE Journal of Solid-State Circuits 31(1):70-76, Jan. 1996.
Canegallo Roberto
Chinosi Mauro
Gozzini Giovanni
Kramer Alan
Rolandi Pier Luigi
Carlson David V.
Fliegel Frederick M.
Nelms David
SGS-Thomson Microelectronics S.R.L.
Tran Andrew Q.
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