Boots – shoes – and leggings
Patent
1996-08-12
1999-03-09
Moise, Emmanuel L.
Boots, shoes, and leggings
36475401, G06F 738, G06F 752
Patent
active
058809813
ABSTRACT:
The present invention contemplates an improved multiplier circuit and method for reducing power consumption by reducing the number of transitions to the input of the multiplier. Each input to the multiplier is fixed for as long as possible by reordering the sequence of the multiplications to take advantage of duplicate input values. The intermediate results of each multiplication are stored in separate accumulators to obtain the final resultants. Power consumption is further reduced through a reduction in the number of transitions on the data bus linking the multiplier and the data register file containing the accumulators.
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Kojima Hirotsugu
Shridhar Avadhani
Hitachi America Ltd.
Moise Emmanuel L.
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