Hardware modeling system and method for simulating portions of e

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371 15, 364578, 364200, 364900, 324 73R, G01R 3128, G06F 1100

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047440848

ABSTRACT:
A hardware modeling system 10 simulates portions of electrical circuits 16, 18 utilizing actual hardware components in the simulation. Access to these hardware modeling elements 16, 18 is provided on a shared basis to plural workstations 14. Simulation vectors for plural users may be stored discontiguously in a first memory 26 and a single user's vectors are transferred to a second memory 28 for streaming to the elements 16, 18. An optional timing analyzer and memory circuit 34 periodically samples outputs from pins of the hardware modeling elements to provide timing information on the response of such elements. High impedance testing and bus contention detection is performed on the pins of the hardware modeling elements. Clocking signals applied to the hardware modeling elements are adjustable and may be set at extremely high frequencies. A special gating circuit 292 accesses each pin of the hardware modeling elements and incorporates one or more of the above features.

REFERENCES:
patent: Re31056 (1982-10-01), Chau et al.
patent: T930005 (1975-01-01), Chia et al.
patent: 3603936 (1971-09-01), Attwood
patent: 3643156 (1972-02-01), Stewart et al.
patent: 3673397 (1972-06-01), Schaefer
patent: 3715573 (1973-02-01), Vogelsberg
patent: 3739349 (1973-06-01), Burdette, Jr. et al.
patent: 3758761 (1973-09-01), Henrion
patent: 3764995 (1973-10-01), Helf, Jr. et al.
patent: 3777129 (1973-12-01), Mehia
patent: 3812337 (1974-05-01), Crosley
patent: 3832535 (1974-08-01), De Vito
patent: 3872441 (1975-03-01), Cailow
patent: 3927371 (1975-12-01), Pomeranz et al.
patent: 3932843 (1976-01-01), Trelut et al.
patent: 4000460 (1976-12-01), Kadakia et al.
patent: 4031517 (1977-06-01), Hirtle
patent: 4044244 (1977-08-01), Foreman et al.
patent: 4066882 (1978-01-01), Esposito
patent: 4070565 (1978-01-01), Borrelli
patent: 4130283 (1979-12-01), Masters
patent: 4156132 (1979-05-01), Hazzard
patent: 4180023 (1979-12-01), Kobayashi
patent: 4196475 (1980-04-01), Hall
patent: 4213175 (1980-07-01), Kurihara
patent: 4213253 (1980-07-01), Gudelis et al.
patent: 4216533 (1980-08-01), Ichimiya et al.
patent: 4228537 (1980-10-01), Henckels et al.
patent: 4236246 (1980-11-01), Skilling
patent: 4242751 (1980-12-01), Henckels et al.
patent: 4300196 (1981-11-01), Lopresti
patent: 4306286 (1981-12-01), Cocke et al.
patent: 4310884 (1982-01-01), Roberts et al.
patent: 4317200 (1982-02-01), Wakatsuki et al.
patent: 4342093 (1982-07-01), Miyoshi
patent: 4348759 (1982-09-01), Scheurmann
patent: 4354268 (1982-10-01), Michel et al.
patent: 4357703 (1982-11-01), Van Brunt
patent: 4370728 (1983-01-01), Coffron
patent: 4397021 (1985-08-01), Lloyd et al.
patent: 4402055 (1983-08-01), Lloyd et al.
patent: 4402055 (1983-08-01), Lloyd et al.
patent: 4404627 (1983-09-01), Marcantonio
patent: 4404635 (1983-09-01), Flaker
patent: 4450560 (1984-05-01), Conner
patent: 4451918 (1984-05-01), Gillette
patent: 4456994 (1974-06-01), Gegarra
patent: 4484329 (1984-11-01), Slamka et al.
patent: 4488299 (1984-12-01), Fellhauer et al.
patent: 4488354 (1984-12-01), Chan et al.
patent: 4493045 (1985-01-01), Hughes, Jr.
patent: 4495642 (1985-01-01), Zellmer
patent: 4500963 (1985-02-01), Smith et al.
patent: 4500993 (1985-02-01), Jacobson
patent: 4510572 (1985-04-01), Reece et al.
patent: 4513384 (1985-04-01), Rosencwaig
patent: 4517661 (1985-05-01), Graf et al.
patent: 4527234 (1985-07-01), Bellay
patent: 4527249 (1985-07-01), Van Brunt
patent: 4527249 (1985-07-01), Van Brunt
patent: 4544882 (1985-10-01), Flora
patent: 4555756 (1985-11-01), Yamanaka
patent: 4587625 (1986-05-01), Marino, Jr. et al.
patent: 4590581 (1986-05-01), Widdoes, Jr.
patent: 4604718 (1986-08-01), Norman et al.
patent: 4607366 (1986-08-01), Stadlmeier et al.
patent: 4613940 (1986-09-01), Shenton et al.
patent: 4620304 (1986-10-01), Faran, Jr. et al.
patent: 4635218 (1987-01-01), Widdoes, Jr.
patent: 4635256 (1987-01-01), Herlein
patent: 4638481 (1987-01-01), Crane et al.
patent: 4644487 (1987-02-01), Smith
patent: 4656632 (1987-04-01), Jackson
Huston, R., "Description of the Intel 8085 Microprocessor Test Programs for the Sentry II/VII With Sequence Processor Module, (Application Note 67)", Nov. 1977, Fairchild Systems Technology.
"Testing a TV Character Generator with the Sentry II Sequence Processor," Application Note 57, Fairchild Systems Technology.
Huston, Robert, "Microprocessor Testing: A Testing Turnaround--Smart DUT Runs the Tester," International Microelectronics Conference, 1975, pp. 16-24.
Huston, R. E., "Microprocessor Testing Equipment Needs," Fairchild Systems Technology, pp. 59-68.
User's Manual, "Terminal Access Simulation and Computation (TASC) System," System Development Corporation, Mar. 1, 1979, pp. 8-1-8-10.
"Selection Guide for Digital Test Program Generation Systems", Submitted by: Henckels, Haas and Brown, Inc., Oct. 25, 1978, pp. 44-45, 179-181, 51, 63.
Koike, Nobuhiko, et al., "A High Speed Logic Simulation Machine," Digest of Papers Compcon 83, Spring, pp. 446-451.
Armstrong, James R. and Woodruff, Garry W., "Chip-Level Simulation of Microprocessors," Jan., 1980, pp. 94-100.
Beaven, P. A. and Brown, D. J., "Simulation and Testing of Three-State Logic Circuitry," IBM Technical Disclosure Bulletin, Sep., 1978, pp. 1662-1663.
Szygenda, Stephen A. and Thompson, Edward W., "Modeling and Design Verification and Diagnosis," IEEE Transactions on Computers, vol. C.25, No. 12, Dec. 1978, pp. 1242-1253.
Sygenda, S. A. and Thompson, E. W., "Digital Logic Simulation in a Time-Based, Table-Driven Environment, Part 1. Design Vertification," Computer, Mar., 1975, pp. 24-36.
Huston, R. E., "Microprocessor Testing Equipment Needs," 1975 Semiconductor Test Symposium, Oct., 1975, pp. 59-68.
"Testing Microprocessor Chips: A Large-scale Challenge," Christos Chrones. Testing Technology, Apr., 1975, pp. 35-42.
Smith, Douglas, H., "Microprocessor Testing--Method or Madness," 1976 Semiconductor Test Symposium, Oct., 1976, pp. 27-29.
Purks, S. R., "Flexibility for Testing Boards Containing LSI Components," article from Gen Rad.
Ulrich, Ernest G., "Exclusive Simulation of Activity in Digital Networks," Computer Systems, Feb., 1969, pp. 102-110.
Allen, Bill and Huber, John, "Configurable State-of-the-Art Logic Analyzer Gives Choice of Performance," Tekweek, Sep., 1981.
Dacier, William C., "Software Generates Tests for Complex Digital Circuits, Electronic Design, Oct. 28, 1982, pp. 137-146.
Timoc, C., et al., "A Novel Approach to Test Generation for VLSI," Digest of Papers Spring Compcon 82., pp. 78-86.
Wadsack, R. L., Logic Testing: An Overview of Simulation and Vector Generation," 1977 Semiconductor Test Symposium,pp. 58-60.
Watson, I. M., et al., "ICTEST: A Unified System for Functional Teting and Simulation of Digital ICs," Digest of Papers 1982 International Test Conference, pp. 499-502.
Pittler, M. S., et al., "System Development and Technology Aspects of the IBM 3081 Processor Complex," IBM Journal of Research and Developmment, Jan., 1982, pp. 2-11.
Roberts, Paul E. and Wolski, Keith T., "Development of a Digital Test Generation System," Computer Aided Design, 1979, pp. 183-186.
Grason, John, "The Impact of a Complex Board Level Circuit on Automatic Test Aids," 1978 Semiconductor Test Conference, pp. 258-263.
Padwick, Gordon C. and Huston, R. E., "Techniques and Equipment for LSI Testing," pp. 56-57.
Read, William R., Jr., "A Hardware Moeling System for MOS LSI Circuits," International Conference on Computer Aided Design, 1983, Digest of Technical Papers, pp. 240-246.
Lessman, Robert A., "Application of Static Automatic Test Program Generators (ATPG) to Dynamic Circuitry," IEEE Autotestcon '81 Proceedings, pp. 361-363.
Lemke, Dick, et al., "Hardware Emulation Conquers the Testing Mountain Created by 16-bit .mu.Ps, " Electronic Design, Jul. 5, 1979, pp. 54-59.
Huston, Robert E., "An Analysis of ATE Testing Costs," 1983 International Test Conference, pp. 396-411.
Magnhager, Bengt, "DIGSIM II, an in Circuit Simulator," IEEE International Conference on Circuits and Computers, ICCC 80, pp. 571-573.
Bowden, Kenneth R., "Design Goals and Implementation Techniques for Time-Ba

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