Static information storage and retrieval – Addressing – Sync/clocking
Patent
1984-05-24
1988-05-10
Hecker, Stuart N.
Static information storage and retrieval
Addressing
Sync/clocking
365227, 365203, G11C 800
Patent
active
047440635
ABSTRACT:
A static memory has an address transition detector, an input data transition detector and a pulse signal generator. When a detector detects that an input address or input data has changed, the pulse signal generator produces a pulse signal having a width longer than the shorter of the data-reading or data-writing cycle. This pulse signal controls the period of time during which a penetrating DC current flows between two power sources via some of the components of the memory.
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"A HI-CMOSII 8K.times.8b Static RAM" 1982 IEEE International Solid-State Circuits Conference, pp. 256-257, (1982). Minato et al.
Konishi et al., "A 64Kb CMOS RAM," IEEE International Solid-State Conference, ISSCC 82, Feb. 12, 1982, pp. 258-259.
Iizuka Tetsuya
Isobe Mitsuo
Ohtani Takayuki
Sakurai Takayasu
Gossage Glenn A.
Hecker Stuart N.
Kabushiki Kaisha Toshiba
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