Video display terminal with paging and scrolling

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Details

340703, 340735, 340750, G06F 314

Patent

active

047440465

ABSTRACT:
Paging and scrolling is provided in a video display terminal having a multi-page video memory by restricting memory access when in the scrolling mode to the page being displayed. An address pager functions as a multiplexer in coupling a central processing unit (CPU) and a cathode ray tube (CRT) controller to the video memory allowing the CPU to designate the mode of operation (paging or scrolling) and the page in memory to be addressed in the scrolling mode of operation, and permits the CRT controller to designate page as well as location to be addressed therein in the paging mode of operation. By limiting display access only to memory locations within a given page while in the scrolling mode, the overlapping and overwriting of adjacent pages of the video memory is avoided. Scrolling is performed by a "wrap-around" feature of each page of the video memory wherein the display information is sequentially displaced upward one horizontal scan line at a time with the erased first line in the video memory corresponding to the uppermost horizontal scan line used to update the bottom scan line with new video information. Paging is accomplished by the CRT controller designating the entire page to be displayed to the video memory. The traditional page addressing scheme may thus be returned to by providing a coded disable signal representing the paging mode of operation to the address pager without the contents of any pages erased or modified during a preceding scrolling operation.

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J. T. Hanna et al., "Storage Paging Device for Microcontrollers", 10/76 IBM, Inc; Technical Disclosure Bulletin, vol. 19, No. 5.

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