Method for designing semiconductor integrated circuit

Details Method for designing semiconductor integrated circuit Method for designing semiconductor integrated circuit

1998-06-09

1999-11-16

Picardat, Kevin M.

Semiconductor device manufacturing: process

Making device array and selectively interconnecting

438142, 438381, H01L 2182

Patent

active

059856998

ABSTRACT:
Cells in which clock skew or variation in transistor properties is to be suppressed are specified and inputted. Next, a method of checking unoccupied cells for arranging dummy cells is specified and inputted. Next, a step of allowing a CAD tool to recognize the unoccupied cells is carried out. In this step, a check is made over a chip so as to see an area in which the cells are not located and to recognize this area as the unoccupied cells. Then, the step of checking whether or not the unoccupied cells are present near the cells to be processed is carried out. In this step, for the cells to be processed, the unoccupied cells are checked by the specified method of checking the unoccupied cells. Then, the dummy cells are arranged in the unoccupied cells.

REFERENCES:
patent: 5512765 (1996-04-01), Gaverick
patent: 5631183 (1997-05-01), Kim et al.
patent: 5691218 (1997-11-01), Colwell et al.

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